An Active Matrix mode display device is a kind of display devices in which display driving of pixels is executed by using Thin Film Transistors (briefly called as TFTs), has the merits of lightness and thinness, lower power consumption, low radiation, low coat and so on, and is the current mainstream display technology.
Active Matrix mode display devices each include a TFT array substrate, and based on the variances in the forming material of a TFT active layer, TFT array substrates can be classified into multiple types, such as, amorphous silicon (a-Si:H), Low Temperature Poly-Silicon (briefly called as LTPS), High Temperature Poly-Silicon (briefly called as HTPS), oxide semiconductor array substrate and so on. A LTPS TFT array substrate has become one of the current research hotspots in the field by virtue of its merits of high carrier mobility, high level of integration capability, strong anti-interference ability, etc.
A LTPS TFT array substrate usually includes a plurality of gate lines in a first direction and a plurality of data lines in a second direction, and the first direction and the second direction are perpendicular to each other, so that a plurality of pixel units arranged in the form of a matrix are defined and formed. As illustrated in FIG. 1, each of the pixel units includes a pixel electrode 115; a storage electrode 104 lying in a lower level than the pixel electrode 115; and a TFT situated at the intersection of a gate line (not illustrated in the figure) and a data line (not illustrated in the figure), which is connected to the pixel electrode 115, and useful for driving the pixel electrode. The TFT includes an active layer 103, a gate electrode 106, a source electrode 110 and a drain electrode 111. In general, the gate electrode 106 is connected to the gate line, the source electrode 106 is connected to the data line, and the drain electrode 111 is connected to the pixel electrode 115.
A method for manufacturing a LTPS TFT array substrate usually includes that, a buffer layer 102, a pattern including an active layer 103 and a storage electrode 104, a gate insulating layer 105, a pattern including a gate electrode 106 and a gate line, an interlayer insulating layer 107, a source contact hole, a drain contact hole, a pattern including a source electrode 110, a drain electrode 111 and a data line, a passivation layer 112, a pixel-electrode contact hole within the passivation layer, a planarizing layer 113, a pixel-electrode contact hole within the planarizing layer 113 (which intercommunicates with the pixel-electrode contact hole within the passivation layer 112), a pixel electrode 115 and a pixel defining layer 116 are formed on a base substrate 101 in sequence. The method further includes the following step: after the pattern including the active layer 103 and the storage electrode 104 is formed, a photoresist pattern by which the active layer 103 is sheltered but the storage electrode 104 is exposed is formed, so as to achieve the ion doping of the storage electrode 104, and then the photoresist pattern is removed.